About this event
Developing FPGA IP using RTL such as VHDL or Verilog is great however the development and verification time can be considerable. In this session we are going to examine how High Level Synthesis can be used to accelerate algorithm development.
In this session we are going to look at
The session will conclude by demonstrating the Integration and test in the hardware showing how to export and build your IP Core in Vivado and how HLS provides not just the IP core but also the drivers needed for SW Development.
Adam Taylor is a chartered engineer and fellow of the Institute of Engineering and Technology. He is an expert in FPGA and Embedded Systems design, with a specialization in high-reliability design. Adam is also a Visiting Professor of embedded systems at the University of Lincoln and loves teaching.
Founded in 2014, Adiuvo Engineering & Training, Ltd. is a consultancy that provides embedded systems design, training, and marketing services. Our aim is to help create better engineering AND better engineers.
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