About this event
Modern FPGA designs contain multiple synchronous and asynchronous clock domains.
Transferring data between these clock domains comes with its own challenges, get it wrong and it can be many hours in the lab, or worse the field trying to determine the root cause.
This webinar is aimed at enabling engineers to be able to understand the challenges which come with designing in a multi-clock environment, and provide the knowledge to be successful in that environment.
As such this webinar is going to address topics such as
This webinar is intended to provide the attendee with a good introduction to CDC, along with understanding of the approaches and mitigation to take during design and implementation to make their design successful.
Webinar is presented in association with Blue Pearl Software and will include demonstrations of the Visual Verification Suite.
Hosted by
Dave Wallace, with 40+ years in EDA, has made significant contributions to physical design, timing verification, logic synthesis, formal verification, layout compaction, hardware linting, and CDC analysis. He holds six U.S. patents, including Blue Pearl Software’s User Grey Cells patent. Dave began in EDA with gate array placement and routing at IBM and has worked at leading companies like HP, Mentor Graphics, Exemplar Logic, Cadence, and Google. An educator at heart, he also ran a tutoring business, aiding 70+ students in Math, Science, and Computer Science. Dave holds a Sc.B. magna cum laude in Math and CS from Brown University and MS/PhD degrees in Computer Science from UC Berkeley, with a Corporate Finance minor at Haas.
Adam Taylor is a chartered engineer and fellow of the Institute of Engineering and Technology. He is an expert in FPGA and Embedded Systems design, with a specialization in high-reliability design.
Founded in 2014, Adiuvo Engineering & Training, Ltd. is a consultancy that provides embedded systems design, training, and marketing services. Our aim is to help create better engineering AND better engineers.
