About this event
One of the most challenging areas in logic design is creating the correct timing constraints.
Get it wrong, and not only does your design not achieve the desired performance, but the implementation time may also take longer. This webinar will examine not only how to define timing constraints which we can use for our AMD FPGAs but also how to investigate and correct timing errors (should they occur).
This webinar will examine the following:
As always, this will be an interactive session with questions and comments encouraged throughout the webinar.
All examples will be presented using AMD Vivado™ Design Suite 2024.1
AMD sponsored this workshop , including engineering hours. AMD, and the AMD Arrow logo, Artix, UltraScale, UltraScale+, Vivado, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
Hosted by
Adam Taylor is a chartered engineer and fellow of the Institute of Engineering and Technology. He is an expert in FPGA and Embedded Systems design, with a specialization in high-reliability design.
Founded in 2014, Adiuvo Engineering & Training, Ltd. is a consultancy that provides embedded systems design, training, and marketing services. Our aim is to help create better engineering AND better engineers.