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SCAN Pattern Validation and Debug - Pre or Post Silicon - [two times available to choose from]

About this event

Taking debug off the tester and back into the design domain saves large amounts of valuable debug time – especially when this can be done both pre or post silicon.  

This can be done with any STIL pattern that is ready for any model of ATE and also with the actual tester patterns for models such as Teradyne Flex, J750, ETS800, Advantest T2000 and V93K

Our guest speaker, Carl Elmen shows how to validate V93K scan patterns by exporting from SmarTest to Verilog and simulating the chip.  

Hosted by

  • Guest speaker
    Ce G
    Carl e Managing Director @ Elmen Consultants

    Carl Elmen is an independent test development consultant with over 15 years experience in the semiconductor industry as a hardware, software and test engineer. He has worked with many leading semiconductor companies and equipment vendors. Currently his main focus is using in-depth debug and optimisation techniques to develop fast, high-quality test programs for Advantest V93K.

  • Team member
    MG T
    Meir Gellis

Test Insight

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